Detailed Description of the Invention
1. Field of the Invention
The present invention relates to a microcomputer capable of preventing leak current produced due to the variation of finished parameters represented by transistor characteristics generated in manufacturing semiconductor products.
2. Description of the Prior Art
An existing microcomputer storing an EPROM (erasable programmable ROM; hereafter referred to as EPROM) has a mode called EPROM mode for writing data in the stored EPROM. The existing microcomputer is designed so that the functions of terminals of the microcomputer will be equivalent to those of the EPROM only and data can be read or written by a general EPROM writer in the EPROM mode. FIG. 3 shows an internal block diagram of the microcomputer in the EPROM mode, where a CPU (central processing unit), RAM (random access memory), and peripheral circuits are omitted because they are separated from the address bs and data bus in the EPROM mode. In FIG. 3, number 1 is a Vcc terminal (first terminal), 2 is a Vpp terminal (second terminal), 3 is a voltage change circuit, 4 is an EPROM control circuit, 5 is a read/write circuit of an EPROM, 6 is the EPROM, 7 is an address decoder circuit, 8 is an address bus, 9 is a data bus, 10 is an EPROM control terminal, 11 is a data input/output terminal, and 12 is an address input terminal. Arrows in FIG. 3 indicate signal flow.
The following is the description of operations in the EPROM mode of the existing microcomputer. When the write voltage Vpp is applied to the Vpp terminal 2, a setting signal thereafter referred to as PGM) (this signal changes from Low level to High level) for executing write setting for the EPROM 6 is outputted to the voltage change circuit 3 and read/write circuit 5 from the EPROM control circuit 4 by setting conditions for writing data in in the internal EPROM to the EPROM control terminal 10. According to the outputted signal, the voltage change circuit 3 in FIG. 4 changes the voltage level of the signal wire C serving as a common wire from from the driving voltage Vcc to the write voltage Vpp and the read/write circuit 5 writes data in the EPROM 6.
The following is the description of the operations of the voltage change circuit 3 by referring to FIG. 4. First, the case is described in which the write voltage Vpp is applied to the Vpp terminal. The threshold values of P-channel transistor, N-channel transistor, and diode are assumed as Vtp, Vtn, and Vtd respectively. And, Va through Vf are assumed as the potential of signal wires "a" through "f" respectively. Because PGM is at Low level in reading data, the N-channel transistor Tr6 is turned off and thereby, the P-channel transistor Tr4 is turned on. In this case, the potential of each signal wire is shown as follows: Va=Vpp-Vtd, Vb=0, Vc=Vcc, Vd=Vpp-Vtd, Ve=Vcc, and Vf=PGM=0.
Because PGM is at High level (at drive voltage Vcc) in writing data, the N-channel transistor Tr6 is turned on and thereby, the P-channel transistor Tr3 is turned on. Also, the N-channel transistor Tr5 is turned off and thereby the P-channel transistor Tr4 is turned off. In this case, the potential of signal wires "a" through "f" is shown as follows:
Va=0, Vb=Vpp-Vtd, Vc=Vpp, Vd=Vpp-Vtd, Ve=0, and Vf=PGM=Vcc. As described above, the potential Vc of the signal wire C serving as a common wire changes to the drive voltage Vcc or write voltage Vpp according to Low or High level of PGM.